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a ad7660 * 16-bit, 100 ksps pulsar unipolar cmos adc information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. rev. d functional block diagram switched cap dac 16 control logic and calibration circuitry clock ad7660 d[15:0] busy rd cs ser/ par ob/ 2c ognd ovdd dgnd dvdd avdd agnd ref refgnd in ingnd pd reset serial port parallel interface cnvst features throughput: 100 ksps inl: 3 lsb max ( 0.0046% of full-scale) 16-bit resolution with no missing codes s/(n+d): 87 db min @ 10 khz, 90 db typ @ 45 khz thd: ?6 db max @ 10 khz analog input voltage range: 0 v to 2.5 v both ac and dc specifications no pipeline delay parallel and serial 5 v/3 v interface spi / qspi/mi crowire/ dsp compatible single 5 v supply operation 21 mw typical power dissipation, 21 w @ 100 sps power-down mode: 7 w max package: 48-lead quad flatpack (lqfp) 48-lead chip scale package (lfcsp) pin-to-pin compatible with the ad7664 applications data acquisition battery-powered systems pcmcia instrumentation automatic test equipment scanners medical instruments process control general description the ad7660 is a 16-bit, 100 ksps, charge redistribution sar, analog-to-digital converter that operates from a single 5 v power supply. the part contains an internal conversion clock, error cor- rection circuits, and both serial and parallel system interface ports. the ad7660 is hardware factory-calibrated and is comprehen- sively tested to ensure ac parameters such as signal-to-noise ratio (snr) and total harmonic distortion ( thd), in addition to the more traditional dc parameters of gain, offset, and linearity. it is fabricated using analog devices?high performance, 0.6 micron cmos process with correspondingly low cost and is available in a 48-lead lqfp and a tiny 48-lead lfcsp with operation specified from ?0 c to +85 c. product highlights 1. fast throughput the ad7660 is a 100 ksps, charge redistribution, 16-bit sar adc with internal error correction circuitry. 2. superior inl the ad7660 has a maximum integral nonlinearity of 3 lsbs with no missing 16-bit code. 3. single-supply operation the ad7660 operates from a single 5 v supply and only di ssipates 21 mw typical. its power dissipation decreases with the throughput to, for instance, only 21 m w at a 100 sps t hroughput. it consumes 7 m w maximum when in power-down. 4. serial or parallel interface versatile parallel or 2-wire serial interface arrangement com- patible with both 3 v or 5 v logic. * patent pending table i. pulsar selection type/ksps 100?50 500?70 800?000 pseudo ad7651 ad7650/ad7652 ad7653 differential ad7660/ad7661 ad7664/ad7666 ad7667 true bipolar ad7663 ad7665 ad7671 true ad7675 ad7676 ad7677 differential 18-bit ad7678 ad7679 ad7674 simultaneous/ ad7654 multichannel ad7655
ad7660especifications (e40 c to +85 c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.) rev. d e2e parameter conditions min typ max unit resolution 16 bits analog input voltage range v in e v ingnd 0v ref v operating input voltage v in e0.1 +3 v v ingnd e0.1 +0.5 v analog input cmrr f in = 25 khz 70 db input current 100 ksps throughput 325 na input impedance see analog input section throughput speed complete cycle 10 m s throughput rate 0 100 ksps dc accuracy integral linearity error e3 +3 lsb 1 differential linearity error e1 +1.75 lsb no missing codes 16 bits transition noise 2 0.75 lsb full-scale error 3 ref = 2.5 v 0.045 0.08 % of fsr unipolar zero error 3 1 5 lsb power supply sensitivity avdd = 5 v 5% 3 lsb ac accuracy signal-to-noise f in = 10 khz 87 90 db 4 f in = 45 khz 90 db spurious-free dynamic range f in = 10 khz 96 db f in = 45 khz 100 db total harmonic distortion f in = 10 khz e96 db f in = 45 khz e100 db signal-to-(noise+distortion) f in = 10 khz 87 db f in = 45 khz 90 db e60 db input 30 db e3 db input bandwidth 820 khz sampling dynamics aperture delay 2ns aperture jitter 5 ps rms transient response full-scale step 8 m s reference external reference voltage range 2.3 2.5 avdd e 1.85 v external reference current drain 100 ksps throughput 22 m a power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 v operating current 100 ksps throughput avdd 3.2 ma dvdd 5 1ma ovdd 5 10 m a power dissipation 5 100 ksps throughput 21 25 mw 100 sps throughput 21 m w in power-down mode 5, 6 7 m w digital inputs logic levels v il e0.3 +0.8 v v ih +2.0 ovdd + 0.3 v i il e1 +1 m a i ih e1 +1 m a digital outputs data format parallel or serial 16-bit pipeline delay conversion results available immediately after completed conversion v ol i sink = 1.6 ma 0.4 v v oh i source = e500 m a ovdd e 0.6 v
rev. d e3e ad7660 parameter conditions min typ max unit temperature range specified performance t min to t max e40 +85 r c notes 1 lsb means least significant bit. with the 0 v to 2.5 v input range, one lsb is 38.15 m v. 2 typical rms noise at worst-case transitions and temperatures. 3 see definition of specifications section. these specifications do not include the error contribution from the external referenc e. 4 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full-scale unless o therwise specified. 5 tested in parallel reading mode. 6 with all digital inputs forced to dvdd or dgnd respectively. specifications subject to change without notice. (e40 c to +85 c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.) timing specifications parameter symbol min typ max unit refer to figures 11 and 12 convert pulsewidth t 1 5ns time between conversions t 2 10 m s cnvst shihd shiha 2 src ad 2 csd ct 2 at rstp rrtirsandpi cnvst datavd 2 datavsd ardatav 2 rt rrtirandsi cs sncvd cs iscvd cs sdtd cnvst sncd sncascd iscp ischihinvsc 2 2 iscinvsc 2 2 sdtvst 22 sdtvht 2 scsncd 2 cs hihsnchi 2 cs hihischi 2 cs hihsdthi 2 shihsrc 2 2 cnvst sncad 2 sncdsd rrtirsand2ssi scst scasdtd 2 sdinst sdinht scp 2 schih sc nts isncscsdtc 2 iscsc s
rev. d ad7660 e4e absolute maximum ratings 1 analog inputs in 2 , ref, ingnd, refgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . avdd + 0.3 v to agnd e 0.3 v ground voltage differences agnd, dgnd, ognd . . . . . . . . . . . . . . . . . . . . . 0.3 v supply voltages avdd, dvdd, ovdd . . . . . . . . . . . . . . . . e0.3 v to +7 v avdd to dvdd, avdd to ovdd . . . . . . . . . . . . . 7 v dvdd to ovdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v digital inputs except the databus d(7:4) . . . e0.3 v to dvdd + 0.3 v databus inputs d(7:4) . . . . . . e0.3 v to ovdd + 0.3 v internal power dissipation 3 . . . . . . . . . . . . . . . . . . . 700 mw internal power dissipation 4 . . . . . . . . . . . . . . . . . . . . . 2.5 w junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 r c storage temperature range . . . . . . . . . . . . e65 r c to +150 r c lead temperature range (soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300 r c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 see analog input section. 3 specification is for device in free air: 48-lead lqfp: q ja = 91 r c/w, q jc = 30 r c/w. 4 specification is for device in free air: 48-lead lfcsp: q ja = 26 r c/w. i oh 500 a 1.6ma i ol to output pin 1.4v c l 60pf * * in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. figure 1. load circuit for digital interface timing pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) agnd cnvst pd reset cs rd dgnd agnd avdd nc dgnd ob/ 2c nc nc ser/ par d0 d1 d2 busy d15 d14 d13 ad7660 d3 d12 d4/ext/ int d5/invsync d6/invsclk d7/rdc/sdin ognd ovdd dvdd dgnd d8/sdout d9/sclk d10/sync d11/rderror nc nc nc nc nc in nc nc nc ingnd refgnd ref nc = no connect t delay t delay 0.8v 0.8v 0.8v 2v 2v 2v figure 2. voltage reference levels for timings caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7660 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide model temperature range package description package option ad7660ast e40 r c to +85 r c quad flatpack (lqfp) st-48 ad7660astrl e40 r c to +85 r c quad flatpack (lqfp) st-48 ad7660acp e40 r c to +85 r cc hip scale (lfcsp) cp-48 AD7660ACPRL e40 r c to +85 r cc hip scale (lfcsp) cp-48 eval-ad7660cb 1 evaluation board eval-control brd2 2 controller board notes 1 this board can be used as a standalone evaluation board or in conjunction with the eval-control brd2 for evaluation/demonstration purposes. 2 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designators.
rev. d ad7660 e5e pin function descriptions pin no. mnemonic type description 1 agnd p analog power ground pin 2 avdd p input analog power pins. nominally 5 v. 3, 6, 7, nc no connect 40e42, 44e48 4 dgnd di must be tied to digital ground 5ob/ 2c di s/tc/ 2c hih s sr/ par di s/psipphih sidatasp 2 d d ppdt sr/ par d di/ sr/ par ppd t/ int sr/ par hihsp t/ int sct/ int hih zsc d di/ sr/ par ppd invsnc sr/ par hihsp sncsnchihhihsnc d di/ sr/ par ppd invsc sr/ par hihspsc is d di/ sr/ par ppd rdc/sdin sr/ par hihsp rt/ int t/ int hihrdc/sdin adcsdtt sdindatasc t/ int rdc/sdinrrdc/sdin hihsdtrdc/sdin sdt nd p i/idp vdd p i/idpn vv dvdd p dpnv 2 dnd p dp 2 d d sr/ par ppd sdt sr/ par hihsp zscctad stdata / 2c ist/ int sdt sc ist/ int hih iinvscsdtsc iinvschihsdtsc
rev. d ad7660 e6e pin function descriptions (continued) pin no. mnemonic type description 22 d9 di/o when ser/ par ppd sc sr/ par hihsp t/ int t sdtinvsc 2 d d sr/ par ppd snc sr /par hihsp zt/ int invsncsnchih hihsdtinvsnc hihsncsdt 2 d d sr/ par ppd rdrrr sr/ par hiht/ int hihsp is rdrrr hih 22 d2 d 2ppdt sr/ par 2 s d thihhih t s dnd p td rd di rd cs rd 2 cs di cs cs rd cs rst di rihihadc pd di pdihih cnvst di sci cnvst hih cnvst t i cnvst and p ta r ai riv rnd ai ria innd ai ai in ai pairvv r nts aiai didi di/d dd pp
rev. d ad7660 e7e definition of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is mea- sured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. full-scale error t he last transition (from 011 . . . 10 to 011 . . . 11 in twos c omplement coding) should occur for an analog voltage 1 1/2 lsb b elow the nominal full scale (2.49994278 v for the 0 ve2.5 v range). the full-scale error is the deviation of the actual level of the last transition from the ideal level. unipolar zero error the first transition should occur at a level 1/2 lsb above analog ground (19.073 m v for the 0 ve2.5 v range). unipolar zero error is the deviation of the actual transition from that point. spurious-free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to s/[n+d] by the following formula: enob = s/ n + d db [] () ? /. 176 602 and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic com ponents to the rms value of a full-scale input signal and is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay aperture delay is a measure of the acquisition performance and is measured from the falling edge of the cnvst tr tad r tadc
rev. d ad7660 e8e etypical performance characteristics code e3 0 inl e lsb 16384 e2 e1 0 1 2 3 32768 49152 65536 tpc 1. integral nonlinearity vs. code code e1.00 0 dnl e lsb 16384 0.00 32768 49152 65536 e0.75 0.50 1.00 1.75 1.50 1.25 0.75 0.25 e0.50 e0.25 tpc 4. differential nonlinearity vs. code frequency e khz 010203 04050 amplitude e db of full scale e180 e120 e40 0 e80 e140 e60 e20 e100 e160 4096 point fft f s = 100khz f in = 45khz snr = 90.14db sinad = 89.94db thd = e101.37db sfdr = 110db tpc 7. fft plot positive inl e lsb 0 0 number of units 0.6 5 10 15 20 25 30 1.2 1.8 2.4 3.0 tpc 2. typical positive inl distribution (350 units) negative inl e lsb 0 0 number of units e0.6 5 10 15 20 25 30 e1.2 e1.8 e2.4 e3.0 35 tpc 5. typical negative inl distribution (350 units) e130 1 thd, harmonics e db 10 100 1000 e90 e80 e60 e70 e100 e120 e110 sfdr thd 60 sfdr e db 90 100 120 110 80 70 second harmonic third harmonic frequency e khz tpc 8. thd, harmonics, and sfdr vs. frequency code e hex 0 counts 8008 8000 7000 6000 5000 4000 3000 2000 1000 0 8009 800a 800b 800c 800d 800e 800f 8010 8011 013 9 0 0 879 1213 7051 7219 tpc 3. histogram of 16,384 conversions of a dc input at the code transition code e hex 0 counts 10000 8000 6000 4000 0 8009 800a 800b 800c 800d 800e 800f 8010 8011 0 188 00 161 2000 9026 3520 3489 tpc 6. histogram of 16,384 conversions of a dc input at the code center input level e db e140 e90 thd, harmonics e db e90 e80 e60 e70 e100 e120 e110 thd second harmonic third harmonic e80 0 e10 e20 e30 e40 e50 e60 e70 e130 tpc 9. thd, harmonics vs. input level
rev. d ad7660 e9e frequency e hz 1 snr and s/(n+d) e db 10 100 1k snr s/(n+d) 13.0 enob e bits 14.5 15.0 16.0 15.5 14.0 13.5 70 85 90 100 95 80 75 enob tpc 10. snr, s/(n+d), and enob vs. frequency sampling rate e sps 10m 0.1 operating currents e na 1m 100k 10k 1k 100 10 1 11 0 100 1k 10k 100k 1m av d d dvdd ovdd tpc 13. operating currents vs. sample rate c l e pf 0 t 12 delay e ns 50 100 200 0 20 30 50 40 10 150 ov dd @ 2.7v, 85 c ov dd @ 2.7v, 25 c ovdd @ 5v, 85 c ovdd @ 5v, 25 c tpc 12. typical delay vs. load capacitance c l e12 e10 e8 e6 e4 e2 0 2 4 6 8 10 12 e55 e35 e15 5 25 45 65 85 105 125 temperature ( c) zero error, full scale error (lsb) full scale error zero error tpc 15. zero error, full scale vs. temperature input level e db e50 snr (referred to full scale) e db e40 e20 0 86 90 92 88 e30 e10 tpc 11. snr vs. input level (referred to full scale) temperature e c e10 e40 power-down operating currents e na 10 60 110 50 60 100 80 20 0 10 e15 35 85 30 40 70 90 dvdd av d d ovdd tpc 14. power-down operating currents vs. temperature
rev. d ad7660 e10e circuit information the ad7660 is a fast, low power, single-supply, precise 16-bit analog-to-digital converter (adc). the ad7660 is capable of converting 100,000 samples per second (100 ksps) and allows power saving between conversions. when operating at 100 sps, for example, it consumes typically only 21 m w. this feature makes the ad7660 ideal for battery-powered applications. the ad7660 provides the user with an on-chip track-and- hold, successive-approximation adc that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. the ad7660 can be operated from a single 5 v supply and be interfaced to either 5 v or 3 v digital logic. it is ho used in a 48-lead lqfp package or a 48-lead lfcsp package that com- bines space savings and allows flexible configurations as either serial or parallel interface. the ad7660 is pin-to-pin compat ible with the ad7664. converter operation the ad7660 is a successive-approximation analog-to-digital converter based on a charge redistribution dac. figure 3 shows t he simplified schematic of the adc. the capacitive dac consists of an array of 16 binary weighted capacitors and an additional lsb capacitor. the comparator?s negative input is connected to a dummy capacitor of the same value as the capacitive dac array. during the acquisition phase, the common terminal of the array tied to the comparator?s positive input is connected to agnd via sw a . all independent switches are connected to the analog input in. thus, the capacitor array is used as a sampling capaci- tor and acquires the analog signal on in input. similarly, the dummy capacitor acquires the analog signal on the ingnd input. when the acquisition phase is complete and the cnvst s a s t rndt ininnd r nd r v r /2v r / v r /t s a adc s s a cp s in r rnd s s s 2c innd c c 2c c c cntr ic sitchs cntr s tpt cd cnvst c adcss
rev. d ad7660 e11e 100nf 10 f 100nf 10 f avdd 10 f 100nf agnd dgnd dvdd ovdd ognd cs rd ser/ par cnvst busy sdout sclk reset pd in ingnd note 2 u1 refgnd c ref note 1 2.5v ref note 1 ref 100 d note 3 clock ad7660 analog input (0v to 2.5v) c/ p/dsp serial port digital supply (3.3v or 5v) analog supply (5v) dvdd ob/ 2c notes 1. with the ad780 or the adr291 voltage reference, c ref is 47 f, see voltage reference input section. 2. the op184 is recommended. 3. optional low jitter cnvst . figure 5. typical connection diagram transfer functions using the ob/ 2c ad tsz v r / vt adtii adccds anainpt v r s v r s s v s sv r / adcit tii ciiv dch a s t d i c srs 22v sr2s 22v s 2v 2v s 22v srs v sr v 2 2 nts tv in v innd v r v rnd 2 tv in v innd tpicacnnctindiara ad
rev. d ad7660 e12e analog input figure 6 shows an equivalent circuit of the input structure of the ad7660. c2 r1 d1 d2 c1 in or ingnd agnd avdd figure 6. equivalent analog input circuit the two diodes d1 and d2 provide esd protection for the analog inputs in and ingnd. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v. this will cause these diodes to become forward-biased and start conducting current. these diodes can handle a forward- biased current of 100 ma maximum. for instance, these conditions could eventually occur when the input buffer?s (u1) supplies are different from avdd. in such cases, an input buffer with a short circuit current limitation can be used to protect the part. this analog input structure allows the sampling of the differen tial signal between in and ingnd. unlike other converters, the ingnd input is sampled at the same time as the in input. by using this differential input, small signals common to both inputs are rejected as shown in figure 7, which represents the typical cmrr over frequency. for instance, by using ingnd to sense a remote signal ground, difference of ground potentials between the sensor and the local adc ground is eliminated. frequency e hz cmrr e db 45 75 10k 10m 1k 1m 80 65 100k 55 85 70 60 50 40 figure 7. analog input cmrr vs. frequency during the acquisition phase, the impedance of the analog input in can be modeled as a parallel combination of capacitor c1 and the network formed by the series connection of r1 and c2. capacitor c1 is primarily the pin capacitance. the resistor r1 is typically 3242 w and is a lumped component made up of some serial resistors and the on resistance of the switches. the capacitor c2 is typically 60 pf and is mainly the adc sampling capaci tor. during the conversion phase, where the switches are opened, the input impedance is limited to c1. it has to be noted that the input impedance of the ad7660, unlike other sar adcs, is not a pure capacitance and thus, inherently reduces the kickback transient at the beginning of the acquisition phase. the r1, c2 makes a one- pole low-pass filter with a typical cutoff frequency of 820 khz that reduces undesirable aliasing effect and limits the noise. when the source impedance of the driving circuit is low, the ad7660 can be driven directly. large source impedances will significantly affect the ac performances, especially the total harmonic distortion (thd). the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades in function of the source impedance and the maximum input frequency as shown in figure 8. input frequency e khz e100 1 100 10 thd e db e95 e90 e85 e80 e75 e70 r s = 500 r s = 100 r s = 50 r s = 20 figure 8. thd vs. analog input frequency and source resistance driver amplifier choice although the ad7660 is easy to drive, the driver amplifier needs to meet at least the following requirements: the driver amplifier and the ad7660 analog input circuit must be able, together, to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). for instance, operation at the maximum throughput of 100 ksps re quires a minimum gain bandwidth product of 5 mhz. the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transi tion noise performance of the ad7660. the noise coming from the driver is filtered by the ad7660 analog input circuit one-pole low-pass filter made by r1 and c2. for instance, a driver with an equivalent input noise of 4 nv/ hz p snr tthd adtpc thd tsnr snr fne loss db n = + ? ? ? ? ? 20 28 784 2 3 2 log () p where: f ? db is the ? db input bandwidth in mhz of the ad7660 (0.82 mhz) or the cutoff frequency of the input filter if any are used. n is the noise factor of the amplifier (1 if in buffer configuration). e n is the equivalent input noise voltage of the op amp in nv/ hz
rev. d ad7660 e13e the ad8519, op162, or the op184 meet these requirements and are usually appropriate for almost all applications. as an alternative, in very high speed and noise-sensitive applications, the ad8021 with an external compensation capacitor of 10 pf or the ad829 with an external compensation capacitor of 82 pf c an be used. this capacitor should have good linearity as an npo ceramic or mica type. moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. voltage reference input the ad7660 uses an external 2.5 v voltage reference. the voltage reference input ref of the ad7660 has a dynamic input impedance; it should therefore be driven by a low im pedance source with an efficient decoupling between ref and refgnd inputs. this decoupling depends on the choice of the voltage reference but usually consists of a 1 m f ceramic capacitor and a low esr tantalum capacitor connected to the ref and refgnd inputs with minimum parasitic inductance. 47 m f is an appropriate value for the tantalum capacitor when used with one of the recommended reference voltages: y the low noise, low temperature drift adr421 and ad780 voltage references y the low power adr291 voltage reference y the low cost ad1582 voltage reference for applications using multiple ad7660s, it is more effective to buffer the reference voltage with a low noise, very stable op amp like the ad8031. care should also be taken with the reference temperature coeffi- cient of the voltage reference that directly affects the full-scale accuracy if this parameter matters. for instance, a 15 ppm/ r c tempco of the reference changes the full scale by 1 lsb/ r c. v ref , as mentioned in the specification table, could be in creased to avdd e 1.85 v. the benefit here is the increased snr obtained as a result of this increase. since the input range is defined in terms of v ref , this would essentially increase the range to make it a 3 v input range with an avdd above 4.85 v. the theoretical improvement as a result of this increase in refer ence is 1.58 db (20 log [3/2.5]). due to the theo retical quantization noise, however, the observed improve ment is ap proximately 1 db. the ad780 can be selected with a 3 v reference voltage. power supply the ad7660 uses three sets of power supply pins: an analog 5 v supply avdd, a digital 5 v core supply dvdd, and a digital input/output interface supply ovdd. the ovdd supply allows direct interface with any logic working between 2.7 v and 5.25 v. to reduce the number of supplies needed, the digital core (dvdd) can be supplied through a simple rc filter from the analog supply, as shown in figure 5. the ad7660 is independent of power supply sequencing and thus free from supply voltage induced latch-up. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 9. input frequency ?hz psrr ?db ?0 1k 10k 100k 1m ?5 ?0 ?5 ?0 ?5 ?0 figure 9. psrr vs. frequency power dissipation vs. throughput the ad7660 automatically reduces its power consumption at the end of each conversion phase. during the acquisition phase, the operating currents are very low, which allows a significant power saving when the conversion rate is reduced, as shown in figure 10. this feature makes the ad7660 ideal for very low power battery applications. it should be noted that the digital interface remains active even during the acquisition phase. to reduce the operating digital supply currents even further, the d igital inputs need to be driven close to the power rails (i.e., dvdd and dgnd for all inputs except ext/ int invsnc i nvscrdc/sdinvddnd thrhptsps prdissipatin pdsr
rev. d ad7660 ?4 conversion control figure 11 shows the detailed timing diagrams of the conversion process. the ad7660 is controlled by the signal cnvst , which initiates conversion. once initiated, it cannot be restarted or aborted, even by the power-down input pd, until the conver- sion is complete. the cnvst signal operates independently of cs and rd signals. cnvst busy mode t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 ac q uire convert acquire convert figure 11. basic conversion timing for a true sampling application, the recommended operation of the cnvst signal is the following: cn vst must be held high from the previous falling edge of busy, and during a minimum delay corresponding to the acquisition time t 8 ; then, when cnvst is brought low, a conversion is initiated and the busy signal goes high until the completion of the conversion. although cnvst is a digital signal, it should be designed with special care with fast, clean edges and levels, with minimum overshoot and undershoot or ringing. for applications where the snr is critical, the cnvst signal should have a very low jitter. this may be achieved by using a dedicated oscillator for cnvst generation or, at least, to clock it with a high frequency low jitter clock, as shown in figure 5. t 9 t 8 reset databus busy cnvst figure 12. reset timing for other applications, conversions can be automatically initi ated. if cnvst is held low when busy is low, the ad7660 controls the acquisition phase and then automatically initiates a new conversion. by keeping cnvst low, the ad7660 keeps the conversion process running by itself. it should be noted that the analog input has to be settled when busy goes low. also, at power-up, cnvst should be brought low once to initiate the conversion process. in this mode, the ad7660 could some- times run slightly faster than the guaranteed limit of 100 ksps. digital interface the ad7660 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. the serial interface is multiplexed on the parallel data bus. the ad7660 digital interface also accommodates both 3 v or 5 v l ogic by simply connecting the ovdd supply pin of the ad7660 to the host system interface digital supply. finally, by using the ob/ 2c input pin, both twos complement or straight binary coding can be used. the two signals cs and rd control the interface. cs and rd have a similar effect because they are together internally. when at least one of these signals is high, the interface outputs are in high impedance. usually, cs allows the selection of each ad7660 in multicircuit applications and is held low in a single ad7660 design. rd is generally used to enable the con- version result on the data bus. t 1 t 3 t 4 t 11 cnvst busy d ata bus cs = rd = 0 t 10 previous conversion data new data figure 13. master parallel data timing for reading (continuous read) parallel interface the ad7660 is configured to use the parallel interface when the ser/ par is held low. the data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as shown, respectively, in figures 14 and 15. when the data is read during the conversion, however, it is recommended that it is read-only during the first half of the conversion phase. this avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. current conversion busy data bus cs rd t 12 t 13 figure 14. slave parallel data timing for reading (read after convert)
rev. d ad7660 e15e previous conversion t 1 t 3 t 12 t 13 t 4 cs = 0 cnvst , rd busy data bus figure 15. slave parallel data timing for reading (read during convert) serial interface the ad7660 is configured to use the serial interface when the ser/ par hihtad ssdttz sc astrsriaintrac ic tad sct/ int tad snc tscsnc t drdc/ sdin s cs rd cnvst snc sc sdt 2 2 2 2 2 2 2 2 22 2 d d d2 d d t/ int rdc/sdin invscinvsnc 2 sdtrrc t/ int rdc/sdin invscinvsnc 2 2 2 2 2 2 2 22 d d d2 d d 2 s cs rd cnvst snc sc sdt sdtrrpcc
rev. d ad7660 e16e usually, because the ad7660 has a longer acquisition phase than the conversion phase, the data is read immediately after conversion. this makes the master read after conversion the most recommended serial mode when it can be used. in this mode, it should be noted that, unlike in other modes, the signal busy returns low after the 16 data bits are pulsed out and not at the end of the conversion phase, which results in a longer busy width. in read-during-conversion mode, the serial clock and data toggle at appropriate instants, which minimizes potential feedthrough between digital activity and the critical conversion decisions. slave serial interface external clock the ad7660 is configured to accept an externally supplied serial data clock on the sclk pin when the ext/ int hihi cs rd t ahih 2 ad ad / t ad s shih dcdrc t a s cs rd ts a a hz ad rdc/sdin t a s cnvst irdc/sdin sc sdtts s sc2ad sps sc sdt rdc/sdin s s data t ad dnstra st cnvst cs sc ad 2 pstra rdc/sdin sdt scin cs in cnvst in cnvst cs taddcc sc sdt d d d d d cs s sdin t/ int invsc 2 2 rd ssdtrrc
rev. d ad7660 e17e external clock data read during conversion figure 20 shows the detailed timing diagrams of this method. during a conversion, while both cs rd t s t rdrrr hih t rdc/sdin hih t hz icrprcssrintracin tad t ad i/ a ad adct ad adsp 2spi d sp sdt cs sc d d d d d 2 2 cnvst s t/ int invsc rd 2 ssdtrrpcc spiiadsp2 2ad spiadsp2t dspad t t t s dsp t spiadsp2 strcpcpcp cphaspiitid spispictt spi adc spisp adsp2 cnvst ad cs s is sc pts sdt sc rd invsc t/ int sr/ par dvdd additinapinsittdrcarit p 2 iadspii
rev. d ad7660 e18e application hints bipolar and wider input ranges in some applications, it is desired to use a bipolar or wider analog input range like, for instance, 10 v, 5 v, or 0 v to 5 v. although the ad7660 has only one unipolar range, by simple modifications of the input driver circuitry, bipolar and wider input ranges can be used without any performance degradation. figure 22 shows a connection diagram that allows this. compo- nent values required and resulting full-scale ranges are shown in table iii. u1 2.5v ref analog input r2 r3 r4 100nf r1 c f u2 c ref in ingnd ref refgnd 100nf ad7660 figure 22. using the ad7660 in 16-bit bipolar and/or wider input ranges table iii. component values and input ranges input range r1 (k w ) r2 ( k w ) r3 ( k w ) r4 ( k w ) 10 v 1 8 10 8 5 v 1 4 10 6.67 0 v to e5 v 1 2 none 0 for bipolar range applications where accurate gain and offset are desired, they can be calibrated by acquiring a ground and a voltage reference using an analog multiplexer u2, as shown in figure 22. also, c f can be used as a one-pole antialiasing filter. layout the ad7660 has very good immunity to noise on the power supplies as can be seen in figure 9. however, care should still be taken with regard to grounding layout. t he printed circuit board that houses the ad7660 should be designed so the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of g round planes that can be easily separated. digital and ana- log ground planes should be joined in only one place, preferably underneath the ad7660, or, at least, as close as possible to the ad7660. if the ad7660 is in a system where multiple devices r equire analog to digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the ad7660. it is recommended to avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane s hould be allowed to run under the ad7660 to avoid noise coupling. fast switching signals like cnvst c t t tad ad d avdddvddvdd asr adc t dvddad avdd vdd dvdd avddrc vdd dvdd tad innd rnd anddndndinnd rnd and adct dnd nd adp a ad vaad adt pcva cntrrd2
rev. d ad7660 e19e 48-lead plastic quad flatpack [lqfp] 1.4 mm thick (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc sq seating plane 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 compliant to jedec standards ms-026bbc 48-lead frame chip scale package [lfcsp] (cp-48) dimensions shown in millimeters pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 bottom view 5.25 5.10 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 sq seating plane paddle connected to agnd. this connection is not required to meet the electrical performances 0.25 min 0.20 ref compliant to jedec standards mo-220-vkkd-2 outline dimensions
rev. d e20e ad7660 c01928e0e10/03(d) revision history location page 10/03?data sheet changed from rev. c to rev. d. update format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to table i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 added pulsar selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 added overvoltage recovery section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 added tpc 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 changes to circuit information section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 changes to figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 renamed table i to table ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 changes to figure 5 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 changes to figure 8 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 changes to driver amplifier choise section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 replaced figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 changes to digital interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 replaced figure 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 deleted figure 22 and renumbered successive figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 replaced microprocessor interfacing section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 changes in bipolar and wider input ranges section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 changes to table iii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 added cp-48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 update outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1/02?data sheet changed from rev. b to rev. c. edits to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to pin function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 edits to driver amplifier choice section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 new voltage reference input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edits to digital interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 new st-48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9/01?data sheet changed from rev. a to rev. b. edit to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edit to timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edit to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edit to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edit to typical performance characteristics graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 10 edit to driver amplifier choice section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edit to figure 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 edit to figure 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 edit to table ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 edit to bipolar and wider input ranges section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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